#ifndef MESSAGE_DEAL_H
#define MESSAGE_DEAL_H

#include "../../global/ObasicTypes.h"
// #include "../fpga_manage.h"
#include "../global.h"


#define SPINAND_FILE_LOGO_NAME "/dev/mtd8"
#define SPINAMD_FILE_KERNEL_NAME "/dev/mtd10" //FKRN

#define FRAME_DATA_LEN  (1024*64 + 20) //数据开buf默认最大+包头长度20个字节

typedef enum{
    UART_4G = 4,
    OVP_COMMUITE_OTHER,

}OVP_COMMUINTE_DEVICE;


typedef enum{

    PHY_HEAD_NUM = 2,				        //定义发送引导字节的长度个数
    PHY_HEAD_VALUE = 0xA5,				    //定义帧头开始时的引导值
    PHY_TRAIL_VALUE = 0x5A,				    //定义帧结尾标志
    PHY_TRANSFER_start_VALUE = 0xA6,		//定义对0xA5的转义
    PHY_TRANSFER_end_VALUE = 0x5B,			//定义对0x5A的转义
    PHY_TRANSFER_FLAG0 = 0x02,				//转义标志1
    PHY_TRANSFER_FLAG1 = 0x01,				//转义标志2


/*接收状态rcv_state*/
    PHY_R_INITIAL_STATE	= 0x00,				//初始状态
    PHY_R_NORMAL_STATE = 0x01,				//正常接收状态
    PHY_R_TRANSFER_STATE1 = 0x02,			//进入接收转义状态1
    PHY_R_TRANSFER_STATE2 = 0x04,			//进入接收转义状态2


/*发送状态send_state*/
    PHY_S_INITIAL_STATE = 0x00,				//初始状态
    PHY_S_PROCEED_STATE = 0x01,				//进入发送状态
    PHY_S_FIRST_STATE = 0x02,				//进入第一个字节发送完状态
    PHY_S_TRANSFER_STATE1 = 0x04,
    PHY_S_TRANSFER_STATE2 = 0x08,
    PHY_S_TRANSFER_STATE3 = 0x10,
    PHY_S_TRANSFER_STATE4 = 0x20,
    PHY_S_END_STATE = 0x40					//发送结束状态
} ONBON_PHY_TRANS;

typedef enum{

    /*PHY获取帧标志rcv_flag*/
     PHY_GF_INVALID = 0x00,//PHY无有效帧
     PHY_GF_VALID = 0x01,  //PHY有效帧
    /*PHY发送标志send_flag*/
     PHY_S_INITIAL_FLAG = 0x00, //初始标志
     PHY_S_START_FLAG = 0x01,	//开始发送标志
     PHY_S_SEND_FLAG = 0x02,    //启动发送标志
     PHY_S_END_FLAG	= 0x03,		//发送完成标志

    /*MCU获取帧标志rcv_valid*/
     MCU_GF_INVALID	= 0x00,	    //MCU无有效帧
     MCU_GF_VALID_FLAG = 0x01,	//MCU有效帧
    /*MCU发送标志send_valid*/
     MCU_SF_INVALID	= 0x00,	    //MCU无有效帧
     MCU_SF_VALID = 0x01,	    //MCU有效帧

    /*记录MCU转发命令*/
     MCU_COMID_INVALID =  0xFF

} OVP_PHY_FLAG;



// #pragma pack (push,1)

typedef struct{
    Ouint16 dstAddr;
    Ouint16 srcAdd;
    Ouint8 protocolType;
    Ouint8 msgSeq;
    Ouint8 controlClass;
    Ouint8 reserved0;
    Ouint8 reserved1;
    Ouint8 cmd;
    Ouint8 data[FRAME_DATA_LEN];
    //Ouint8 calxor;

}PhyData_Type;

// #pragma pack(pop)

#define  PC_WIFI_LAN_UART_SAME 1

#if PC_WIFI_LAN_UART_SAME
 #define  PC_INTERFACE_NUM    2
 #else
 #define  PC_INTERFACE_NUM    0
#endif


typedef enum{
    UARTNUM = (5),	     //num of communite
    UART_DSP = (0),
    UART_PC  =  (1),
    UART_WIFI = (2),	 //WIFI
    WLAN_PC = (3),       //net
    PC_FPGA_SPI = (4),    //pc to fpga

    //fpga net txc cache
    //0-DSP 1-PC 2-FPGA
    FPGA_SPI = (2)

} OVP_COMMUNITE;



typedef enum
{
    FRAME_DST_ADDR_L = 0x00,
    FRAME_DST_ADDR_H = 0x01,
    FRAME_SEQUENCE_NUMBER = 0x05,
    FRAME_CONTROL_CLASS = 0x06,
    FRAME_NETPORT  = 0x07,    //net port
    FRAME_CMD = (0x09)          //cmd offset

}OVP_FRAME_HEAD_TYPE;


typedef enum{
    CONTROL_CLASS_TXC = 0x00,
    CONTROL_CLASS_RCV = 0x01,
    CONTROL_CLASS_MULTCARD = 0x03,
    CONTROL_CLASS_WILDCARD = 0xff //通配符

}OVP_CONTROL_CLASS_TYPE;

typedef enum
{
    RAM_LIST_DEVICE_INFO_ADDR = 0x00600440,
    RAM_LIST_DEVICE_CODE_L = 0x0000,//0x6C52,
    RAM_LIST_DEVICE_CODE_H = 0x0001,//0x6C52,
    RAM_LIST_DEVICE_TEMP_L = 0x0002,//0x0019,
    RAM_LIST_DEVICE_TEMP_H = 0x0003,//0x0019,
    RAM_LIST_DEVICE_VOL_L = 0x0004,//0x000C,
    RAM_LIST_DEVICE_VOL_H = 0x0005,//0x000C,
    RAM_LIST_DEVICE_FAN_L = 0x0006,//0x0001,
    RAM_LIST_DEVICE_FAN_H = 0x0007,//0x0001,

    RAM_LIST_DEVICE_INPUT_CARD_CRC_L = 0x0010,//0x0002,
    RAM_LIST_DEVICE_INPUT_CARD_CRC_H = 0x0011,//0x0002,
    RAM_LIST_DEVICE_INPUT_1_L = 0x0012,//0x0001,
    RAM_LIST_DEVICE_INPUT_1_H = 0x0013,//0x0001,
    RAM_LIST_DEVICE_INPUT_2_L = 0x0014,//0x0001,
    RAM_LIST_DEVICE_INPUT_2_H = 0x0015,//0x0001,

    RAM_LIST_DEVICE_OUTPUT_CARD_CRC_L = 0x0026,//0x0002,
    RAM_LIST_DEVICE_OUTPUT_CARD_CRC_H = 0x0027,//0x0002,
    RAM_LIST_DEVICE_OUTPUT_1_L = 0x0028,//0x0001,
    RAM_LIST_DEVICE_OUTPUT_1_H = 0x0029,//0x0001,
    RAM_LIST_DEVICE_OUTPUT_2_L = 0x002A,//0x0001,
    RAM_LIST_DEVICE_OUTPUT_2_H = 0x002B,//0x0001,

    RAM_LIST_INPUT1_L = 0x0040,
    RAM_LIST_INPUT1_H = 0x0041,
    RAM_LIST_INPUT2_L = 0x0042,
    RAM_LIST_INPUT2_H = 0x0043,

    RAM_LIST_OUTPUT1_L = 0x0060,
    RAM_LIST_OUTPUT1_H = 0x0061,
    RAM_LIST_OUTPUT2_L = 0x0062,
    RAM_LIST_OUTPUT2_H = 0x0063

}RAM_LIST_DEVICE_INFO;


//about the RAM LIST
#define RAM_LIST_LCD_SCREEN_DESCRIPE  0x00800000
#define RAM_LIST_LCD_SCREEN_DATA      0x00800080
#define RAM_LIST_INPUT_DESCROPTE      0x00600000

#define RAM_LIST_COMMUNITE_STATUS_START   0x00600880
#define RAM_LIST_COMMUNITE_STATUS_END     0x00600C80
#define RAM_LIST_MCU_FUN              0x00600040
    #define RAM_FUNC_LCD_L         0x00
    #define RAM_FUNC_LCD_H         0x01
    #define RAM_FUNC_MODE_L        0x02
    #define RAM_FUNC_MODE_H        0x03
    #define RAM_MAX_LED_WIDTH_L    0x04
    #define RAM_MAX_LED_WIDTH_H    0x05
    #define RAM_MAX_LED_HEIGHT_L   0x06
    #define RAM_MAX_LED_HEIGHT_H   0x07
    #define RAM_MIN_LED_WIDTH_L    0x08
    #define RAM_MIN_LED_WIDTH_H    0x09
    #define RAM_MIN_LED_HEIGHT_L   0x0A
    #define RAM_MIN_LED_HEIGHT_H   0x0B
    #define RAM_MAX_LED_TOTAL_L1   0x0C
    #define RAM_MAX_LED_TOTAL_L2   0x0d
    #define RAM_MAX_LED_TOTAL_L3   0x0e
    #define RAM_MAX_LED_TOTAL_L4   0x0f
    #define RAM_MAX_IMG_QUALITY_L  0x10
    #define RAM_MAX_IMG_QUALITY_H  0x11
    #define RAM_PLAN_TASK_MODE_L   0x12
    #define RAM_PLAN_TASK_MODE_H   0x13
    #define RAM_TIMING_TASK_MODE_L 0x14
    #define RAM_TIMING_TASK_MODE_H 0x15
    #define RAM_USB_PLAY_MODE_L    0x16
    #define RAM_USB_PLAY_MODE_H    0x17
    #define RAM_TASK_NUM_MODE_L    0x18
    #define RAM_TASK_NUM_MODE_H    0x19
    #define RAM_CYCLE_LIST_L       0x1A
    #define RAM_CYCLE_LIST_H       0x1B
    #define RAM_WINDOW_NUM_L       0x1C
    #define RAM_WINDOW_NUM_H       0x1D
    #define RAM_CROP_SOURCE_NUM_L  0x1E
    #define RAM_CROP_SOURCE_NUM_H  0x1F
    #define RAM_SIGNAL_LOAD_WIN_L  0x20
    #define RAM_SIGNAL_LOAD_WIN_H  0x21
    #define RAM_OCH_MAX_L          0x22
    #define RAM_OCH_MAX_H          0x23
    #define RAM_OUT_SPLICE_L       0x24
    #define RAM_OUT_SPLICE_H       0x25
    //#define RAM_
    #define RAM_WIN_LAYOUT_MODE_L  0x28
    #define RAM_WIN_LAYOUT_MODE_H  0x29
    #define RAM_OSD_MAX_L          0x2A
    #define RAM_OSD_MAX_H          0x2B
    #define RAM_OSD_TYPE_L         0x2C
    #define RAM_OSD_TYPE_H         0x2D
    #define RAM_SPLIC_SOURCE_L     0x2E
    #define RAM_SPLIC_SOURCE_H     0x2F
    #define RAM_LCD_SIZE_W_L       0x32
    #define RAM_LCD_SIZE_W_H       0x33
    #define RAM_LCD_SIZE_H_L       0x34
    #define RAM_LCD_SIZE_H_H       0x35
    #define RAM_4G_ONLINE_STATUS   0x36


#define RAM_LIST_USER_MODE_START   0x1000
#define RAM_LIST_USER_MODE_END     0x11000
#define RAM_LIST_OTHER_CHIP_VER    0xFD000000
#define RAM_LIST_331_DUMP_START    0xFE000000
#define RAM_LIST_331_DUMP_END    0xFF000000

typedef enum{
    //about phy addr
    FPGA_DEFAULT_ADDR = 0xF000,
    FPGA_MAX_ADDR = 0xF00F,
    PC_DEFAULT_ADDR = 0xF010,				        //PC default
    MCU_DEFAULT_ADDR = 0xF100,				        //MCU default
    MCU_DEFAULT_ADDR1 = 0xF101,				        //MCU default 1
    MCU_MAX_ADDR = 0xF1FF,				        //MCU max default
    DSP_DEFAULT_ADDR = 0xF200,				        //DSP default
    DSP_DEFAULT_ADDR1 = 0xF201,				        //DSP default 1
    DSP_MAX_ADDR = 0xF2FF	                                //DSP max addr

} OVP_PRO_SRC_DES_ADDR;





#define ENABLE_OUT2_DELAY_ 0
#define FPGA_SPI_CS_TYPE  0 //1--one cmd cs  /1 --one word cs


typedef enum {
    CONTROL_CLASS_MCU = 0x08,
    CONTROL_CLASS_FPGA = 0x00

} ONBON_CONTROL_CLASS_Type ;


typedef enum{
    ERASE_TYPE_4K = (0x01),	     //4k
    ERASE_TYPE_32K = (0x02),	 //32k
    ERASE_TYPE_64K = (0x04),	 //64K
    ERASE_TYPE_ALL = (0x08)	     //flash chip

} ONBON_FLASH_ERASE_TYPE;



typedef enum {
    CMD_ACK_NOERR = 0x00,           //!<ack无错误
    CMD_NACK_EXECUTION = 0x01,      //!<当前命令执行失败
    CMD_NACK_CRC16 = 0x02,          //!<CRC校验错误
    CMD_NACK_PROTOCAL = 0x03,       //!<协议版本号错误
    CMD_NACK_GROUP = 0x04,          //!<命令组错误
    CMD_NACK_COMMAND = 0x05,        //!<命令错误
    CMD_NACK_FLASH_ERASE = 0x06,	//!<flash 擦除错误
    CMD_NACK_FLASH_WRITE = 0x07, 	//!<flash 写错误

    CMD_NACK_PASS_ERROR   =      0x0a,
    CMD_NACK_UID_ERROR    =      0x0B,
    CMD_NACK_LOCK_ERROR   =      0x0C
} ONBON_OVP_ACK_STATUS ;


enum
{
    CMD_RAM_W_SINGLE_PARA = 0x31, //signal write
    CMD_RAM_DSP_GROUP = 0xB0,

    CMD_RAM_WRITE = 0x60,        //ram write
    CMD_RAM_READ = 0x61,         //ram read
    CMD_GET_CARD_UID = 0x83,	 // UID
    CMD_START_UPDATE = 0x84,     //update
    CMD_ADJUST_TIME = 0x87,      //write rtc
    CMD_TEST_88 = 0X88,
    CMD_PARAM_SAVE = 0x81,
    CMD_GET_CARD_VERSION = 0x82, //get version

    //about flash
    CMD_FLASH_ERASE = 0x70,     //erase flash
    CMD_FLASH_WRITE	= 0x71,     //write flash
    CMD_FLASH_READ = 0x72,      //read flash

    //
    CMD_REGISTER_WRITE = 0xA0,   //reg write
    CMD_REGISTER_READ = 0xA1,    //reg read

    //
    CMD_BARCODE_ID = 0xA2,       //about BarcodeId
    CMD_SET_BARCODE = 0x1E,      //set barcode
    CMD_READ_BARCODE = 0x1F,     //read barcode

    //
    CMD_NET_ETH_GROUP = 0xA4,    //net search
    CMD_NET_ETH_SET_MAC = 0x00,  //mac set
    CMD_NET_ETH_SET_IP = 0x01,   //ip set
    CMD_NET_ETH_SEARCH = 0x03,   //net search
    CMD_NET_ETH_GET_INFO = 0x10, //m_info search

    //
    CMD_WRITE_FILE_GROUP = 0xC0, //write file group
    CMD_WRITE_FILE_START =0x01,  //start to write
    CMD_WRITE_FILE_BLOCK = 0x02, //write block file
    CMD_WRITE_FILE_END =0x03,    //end to write
    CMD_READ_FILE_START = 0x04,  //start to read
    CMD_READ_FILE_BLOCK = 0x05,
    CMD_READ_FILE_END = 0x06,
    CMD_WRITE_DEFINED_FILE_START = 0x07, //start to write defined file
    CMD_READ_DEFINED_FILE_START = 0x08,  //start to read defined file
    CMD_READ_DIR_FILE_PARA = 0x09, // start to read files
    CMD_DELETE_FILE = 0x0a,  //delete file
    //

    //!<特殊参数命令组
    CMD_LOCK_TIME             =      0xC3,    //!<工程锁命令
    CMD_PROJECT_PROBATION     =      0x00,    //!<试用期变更
    CMD_PROJECT_REGULAR       =      0x01,    //!<试用期转正
    CMD_PROJECT_PASSWORD      =      0x02,    //!<密码修改
    CMD_PROJECT_SET           =      0x06,    //!<工程运行时间设置
    CMD_PROJECT_GET           =      0x07,    //!<获取工程锁参数
    CMD_PROJECT_CHECKWORD     =      0x08,    //!<密码校验
    CMD_ENGINEERING_LOCK      =      0x09,    //!<工程锁锁定
    CMD_ENGINEERING_UNLOCK    =      0x0A,    //!<工程锁解锁

    //!<4G模块命令组
    CMD_4G_MODULE_GROUP       =      0xC4,    //!<4G模块命令组
    CMD_4G_CHECKLINK          =      0x00,    //!<检查连接
    CMD_4G_SETPROPERTY        =      0x01,    //!<设置属性
    CMD_4G_GETPROPERTY        =      0x02,    //!<获取属性
    CMD_4G_SENDFILE           =      0x03,    //!<发送文件
    CMD_4G_SENDFILEDATA       =      0x04,    //!<发送文件数据
    CMD_4G_SENDFILEEND        =      0x05,    //!<发送文件结束
    CMD_4G_SENDFILECANCEL     =      0x06,    //!<发送文件取消
    CMD_4G_RECVFILE           =      0x07,    //!<获取文件
    CMD_4G_RECVFILEDATA       =      0x08,    //!<获取文件数据
    CMD_4G_RECVFILEEND        =      0x09,    //!<获取文件结束
    CMD_4G_RECVFILECANCEL     =      0x0A,    //!<获取文件取消
    CMD_4G_CHECKONLINE        =      0x0B,    //!<检查在线
    CMD_4G_FORMATSD           =      0x0C,    //!<格式化SD
    CMD_4G_VERIFYCA           =      0x0D,    //!<证书验证


    //
    CMD_SEARCH_GROUP = 0x10,     //search
    //
    CMD_RCV_BIND_GROUP = 0x39,

    SOURCE_INFO = 4,
    CROP_INFO = 5,
    EDID_INFO = 6,
    OPTIONS_INFP = 7,
    USER_DATA_INFO = 8
};



typedef enum{
    OVP_RCV_LOCK_ACT_ZERO = 0,   //默认初始化0
    OVP_RCV_LOCK_ACT_CANCLE = 1, //执行完毕
    OVP_RCV_LOCK_ACT_ATONCE = 2, //执行一次
    OVP_RCV_LOCK_AT_ONCE_LOCK = 8, //立即锁定
    OVP_RCV_LOCK_DELAY_TRIAL = 9,//延长试用
    OVP_RCV_LOCK_IMMEDIATE_PROBATION = 10, //立即转正
    OVP_RCV_LOCK_CHANGE_PASSWORD = 12, //立即转正
    OVP_RCV_LOCK_OVER

}OVP_RCV_LOCK_STATUS;

class message_deal
{
public:
    message_deal();
    ~message_deal();


    Ouint32 write_ram(Ouint8 *Rcv);
    Ouint32 read_ram(Ouint8 *Rcv);
    Ouint32 param_save(Ouint8 *Rcv);
    Ouint32 get_card_version(Ouint8 *Rcv);
    Ouint32 start_update(Ouint8 *Rcv,Ouint32 len);

    Ouint32 message_group_deal(Ouint8 *Rcv ,Ouint32 le ,Ouint8 comm_id);
    Ouint32 write_rtc_time(Ouint8 *Rcv) ;
    Ouint32 write_file_group(Ouint8 *Rcv);
    Ouint32 write_file_start(Ouint8 *Rcv);
    Ouint32 write_defined_file_start(Ouint8 *Rcv);
    Ouint32 write_file_block(Ouint8 *Rcv);
    Ouint32 write_file_end(Ouint8 *Rcv);
    Ouint32 read_file_start(Ouint8 *Rcv);
    Ouint32 read_defined_file_start(Ouint8 *Rcv);
    Ouint32 read_file_block(Ouint8 *Rcv);
    Ouint32 read_file_end(Ouint8 *Rcv);
    Ouint32 read_dir_file_para(Ouint8 *Rcv);
    Ouint32 delete_file_name(Ouint8 *Rcv);
    Ouint32 project_lock_group(Ouint8 *Rcv, Ouint8 comm_id);
    Ouint32 write_register(Ouint8 *Rcv);
    Ouint32 read_register(Ouint8 *Rcv);

    Ouint8 is_super_password(Ouint8* password);
    Ouint8 set_new_project_time(Ouint8 type , TimeRealType* rev_time , Ouint8* password ,Ouint8 comm_id);
    Ouint16 cmd_erase_flash(Ouint8 *Rcv);
    Ouint16 cmd_write_flash(Ouint8 *Rcv);
    Ouint16 cmd_read_flash(Ouint8 *Rcv);
    Ouint16 project_lock_probation(Ouint8 *Rcv_messag,Ouint8 comm_id);
    Ouint16 project_lock_change(Ouint8 *Rcv_messag,Ouint8 comm_id);
    Ouint16 project_lock_password(Ouint8 *Rcv_messag,Ouint8 comm_id);
    Ouint16 project_lock_set(Ouint8 *Rcv_messag,Ouint8 comm_id);
    Ouint16 project_lock_get(Ouint8 *Rcv_messag,Ouint8 comm_id);
    Ouint16 project_lock_checkword(Ouint8 *Rcv_messag,Ouint8 comm_id);
    Ouint16 project_engineering_lock(Ouint8 *Rcv_messag,Ouint8 comm_id);
    Ouint16 project_engineering_unlock(Ouint8 *Rcv_messag,Ouint8 comm_id);
    Ouint32 get_card_uid(Ouint8 *Rcv);

    void Time_to_RAM(void);
    void FPGA_Ex_ram_update(void);


    Ouint8 rcv_state;
    Ouint8 send_state;
    Ouint32 data_transf_meaning(Ouint8 *sData, Ouint8 *cmdBuf,Ouint32 len,Ouint8 *frame_status) ;
    Ouint32 data_re_transf_meaning(Ouint8 *sData, Ouint8 *cmdBuf,Ouint32 len,Ouint8 *frame_status);
    void swap_phy_head(Ouint8 *cmdBuf) ;

    //Ouint8 fileBuf_onbon[384*1024];
//public slots:
//    void slot_update_timer_ticks(void) ;
    //message_deal_4g* p_message_deal_4g;
};


static Ouint8 const super_password[16] = {0x32,0x1f,0x39,0x4a,0xef,0xf9,0xa8,0x2c,0xc1,0x39,0x27,0x71,0xf3,0xd1,0xbb,0x60};


#endif
